There is known a semiconductor integrated circuit device which has a plurality of circuits that requires a clock signal (see Patent Document 1, for example). The semiconductor integrated circuit device is provided with a clock trunk line from a pulse generator and a clock driver, a power supply and a ground line, a shield wiring for clock trunk line, and a plurality of circuits. Further, the semiconductor integrated circuit device is provided with a connecting means in a region where a clock branch line and a shield wiring for clock branch line are provided and the shield wiring for clock branch line and either one of the power supply and the ground line intersect with each other, which connecting means connects the both depending on a judgment result obtained by judging whether or not each disposition relationship of components of the device fulfils a predetermined rule.
There is also known a clock wiring structure which includes: a clock wiring to propagate a clock signal which clock wiring is provided in a layer; a pair of same-layer shield wirings provided on both sides along the clock wiring in the layer; and an adjacent-layer wiring provided along the clock wiring and the pair of shield wirings in a lower layer and an upper layer of the layer or in either one of these layers (see Patent Document 2, for example).
Further, there is known a wiring structure which has: a clock wiring; a pair of first shield wirings provided on both sides along the clock wiring in the same layer as that of the clock wiring; and a second shield wiring provided in a manner to cover a region which faces the clock wiring and the pair of first shield wirings in a different layer from that of the clock wiring via an insulating layer (see Patent Document 3, for example). The wiring structure has an MIM capacitor in which a pair of electrodes are disposed to face via an insulating layer, and at least one of the pair of electrodes of the MIM capacitor is provided in the same layer as that of the second shield wiring.
(Patent Document 1) Japanese Laid-open Patent Publication No. 2001-308189
(Patent Document 2) Japanese Laid-open Patent Publication No. 2003-158186
(Patent Document 3) Japanese Laid-open Patent Publication No. 2009-218526
In a case where a plurality of clock signal lines are disposed and the same clock signal is distributed by a clock time, a lag occurs in timings of a plurality of distributed clock signals if capacitances of the plural clock lines are different, and a clock skew occurs.